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this is information on a product in full production. june 2014 docid024975 rev 2 1/53 lsm303c ultra-compact high-performance ecompass module: 3d accelerometer and 3d magnetometer datasheet - production data features ? 3 magnetic field channels and 3 acceleration channels ? 16 gauss magnetic full scale ? 2/4/8 g selectable acceleration full scale ? 16-bit data output ? spi / i 2 c serial interfaces ? analog supply voltage 1.9 v to 3.6 v ? power-down mode / low-power mode ? programmable interrupt generators for free- fall, motion detection and magnetic field detection ? embedded temperature sensor ? embedded fifo ? ecopack ? , rohs and ?green? compliant applications ? tilt-compensated compasses ? map rotation ? position detection ? motion-activated functions ? free-fall detection ? click/double-click recognition ? pedometer ? intelligent power saving for handheld devices ? display orientation ? gaming and virtual reality input devices ? impact recognition and logging ? vibration monitoring and compensation description the lsm303c is a system-in-package featuring a 3d digital linear acceleration sensor and a 3d digital magnetic sensor. the lsm303c has linear acceleration full scales of 2 g / 4 g / 8 g and a magnetic field full scale of 16 gauss . the lsm303c includes an i 2 c serial bus interface that supports standard and fast mode (100 khz and 400 khz) and an spi serial standard interface. the system can be configured to generate an interrupt signal for free-fall, motion detection and magnetic field detection. the magnetic and accelerometer blocks can be enabled or put into power-down mode separately. the lsm303c is available in a plastic land grid array package (lga) and is guaranteed to operate over an extended temperature range from -40 c to +85 c. lga-12 (2.0x2.0x1.0 mm) table 1. device summary part number temperature range [c] package packaging lsm303c -40 to +85 lga-12 tray LSM303CTR -40 to +85 lga-12 tape and reel www.st.com
contents lsm303c 2/53 docid024975 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 linear acceleration sensor sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 magnetic sensor sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 zero-gauss level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.5 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.6 bypass-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.7 retrieving data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.8 fifo multiple read (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 activity/inactivity function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid024975 rev 2 3/53 lsm303c contents 53 4.4 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 high current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.1 accelerometer spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.2 accelerometer spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.3 magnetometer spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.4 magnetometer spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 who_am_i_a (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 act_ths_a (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 act_dur_a (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.4 ctrl_reg1_a (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.5 ctrl_reg2_a (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6 ctrl_reg3_a (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.7 ctrl_reg4_a (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.8 ctrl_reg5_a (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.9 ctrl_reg6_a (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.10 ctrl_reg7_a (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.11 status_reg_a (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.12 out_x_l_a (28h), out_x_h_a (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.13 out_y_l_a (2ah), out_y_h_a (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.14 out_z_l_a (2ch), out_z_h_a (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.15 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.16 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.17 ig_cfg1_a (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
contents lsm303c 4/53 docid024975 rev 2 8.18 ig_src1_a (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.19 ig_ths_x1_a (32h), ig_ths_y1_a (33h), ig_ths_z1_a (34h) . . . . . 41 8.20 ig_dur1_a (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.21 ig_cfg2_a (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.22 ig_src2_a (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.23 ig_ths2_a (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.24 ig_dur2_a (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.25 xl_reference (3ah), xh_reference (3bh) . . . . . . . . . . . . . . . . . 43 8.26 yl_reference (3ch), yh_reference (3dh) . . . . . . . . . . . . . . . . . 43 8.27 zl_reference (3eh), zh_reference (3fh) . . . . . . . . . . . . . . . . . . 43 8.28 who_am_i_m (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.29 ctrl_reg1_m (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.30 ctrl_reg2_m (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.31 ctrl_reg3_m (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.32 ctrl_reg4_m (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.33 ctrl_reg5_m (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.34 status_reg_m (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.35 out_x_l_m (28h), out_x_h_m(29h) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.36 out_y_l_m (2ah), out_y_h_m (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.37 out_z_l_m (2ch), out_z_h_m (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.38 temp_l_m(2eh), temp_h_m (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.39 int_cfg_m (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.40 int_src_m (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.41 int_ths_l_m (32h), int_ths_h_m (33h) . . . . . . . . . . . . . . . . . . . . . . 49 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
docid024975 rev 2 5/53 lsm303c list of tables 53 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. activity/inactivity function control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 25 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25 table 16. sad + read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. sad + read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. accelerometer register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 19. magnetic sensor register address map: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. who_am_i_a register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 21. act_ths_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. act_dur_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 23. ctrl_reg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 24. ctrl_reg1_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 25. odr register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 26. low-pass cutoff frequency in high-resolution mode (hr = 1). . . . . . . . . . . . . . . . . . . . . . . 34 table 27. ctrl_reg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 28. ctrl_reg2_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. ctrl_reg3_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 30. ctrl_reg3_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 31. ctrl_reg4_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32. ctrl_reg4_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 33. ctrl_reg5_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 34. ctrl_reg5_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 35. self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 36. ctrl_reg6_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 37. ctrl_reg6_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 38. ctrl_reg7_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 39. ctrl_reg7_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 40. status_reg_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 41. status_reg_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 42. out_x_l_a register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 43. out_x_h_a register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 44. out_y_l_a register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 45. out_y_h_a register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 46. out_z_l_a register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 47. out_z_h_a register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 48. fifo_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables lsm303c 6/53 docid024975 rev 2 table 49. fifo_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 50. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 51. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 52. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 53. ig_cfg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 54. ig_cfg1_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 55. ig_src1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 56. ig_src1_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 57. ig_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 58. ig_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 59. ig_dur1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 60. ig_dur1_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 61. ig_cfg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 62. ig_cfg2_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 63. ig_src2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 64. ig_src2_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 65. ig_ths2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 66. ig_ths2_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 67. ig_dur2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 68. ig_dur2_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 69. who_am_i_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 70. ctrl_reg1_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 71. ctrl_reg1_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 72. x and y axes operative mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 73. output data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 74. ctrl_reg2_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 75. ctrl_reg2_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 76. full-scale selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 77. ctrl_reg3_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 79. system operating mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 78. ctrl_reg3_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 80. ctrl_reg4_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 81. ctrl_reg4_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 82. z-axis operative mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 83. ctrl_reg5_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 84. ctrl_reg5_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 85. status_reg_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 86. status_reg_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 87. int_cfg_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 88. int_cfg_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 89. int_src_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 90. int_src_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 91. int_ths_l_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 92. int_ths_h_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 93. lga-12 2x2x1 mm mechanical dimensions (see note 1 and 2) . . . . . . . . . . . . . . . . . . . . . 50 table 94. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
docid024975 rev 2 7/53 lsm303c list of figures 53 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. i 2 c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. fifo multiple read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. lsm303c electrical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 9. accelerometer spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 10. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. accelerometer spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. magnetometer spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 13. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. magnetometer spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. lga-12 2x2x1 mm mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
block diagram and pin description lsm303c 8/53 docid024975 rev 2 1 block diagram and pin description 1.1 block diagram figure 1. block diagram i (m) y+ z+ y- z- x+ x- charge amplifier control a/d converter mux logic charge amplifier y+ z+ y- z- a x+ x- i2c spi cs_xl cs_mag scl/spc int_xl clock trimming circuits reference self test a/d converter int_mag mux control logic temp. sensor fifo drdy_mag sda/sdi/sdo
docid024975 rev 2 9/53 lsm303c block diagram and pin description 53 1.2 pin description figure 2. pin connections x 1 y z vdd_io sc l/spc sda/sdi/sdo cs sdo/sa0 res gnd int1 int2 res vdd res (bottom view) pin 1 indicator 4 1 5 7 11 8 res res 12 14 gnd sc l/spc sda/sdi/sdo cs_xl cs_mag gnd c1 int_xl vdd_io ( bottom view ) 4 1 5 6 int_mag 11 drdy_mag 7 10 vdd direction of detectable magnetic fields top view x z y direction of detectable accelerations top view 12
block diagram and pin description lsm303c 10/53 docid024975 rev 2 table 2. pin description pin# name function 1 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 2 cs_xl accelerometer: spi enable i 2 c/spi mode selection 1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled 3 cs_mag magnetometer: spi enable i 2 c/spi mode selection 1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled 4 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 5 c1 capacitor connection (c1 = 100 nf) 6 gnd connected to gnd 7 int_mag magnetometer interrupt signal 8 gnd connected to gnd 9 vdd power supply 10 vdd_io power supply for i/o pins 11 drdy_mag magnetometer data ready 12 int_xl accelerometer interrupt signal
docid024975 rev 2 11/53 lsm303c module specifications 53 2 module specifications 2.1 sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 2.5 v. the operational power supply range is from 1.9 v to 3.6 v. table 3. sensor characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) 2 g 4 8 m_fs magnetic measurement range 16 gauss la_so linear acceleration sensitivity linear acceleration fs = 2 g 0.061 m g /lsb linear acceleration fs = 4 g 0.122 linear acceleration fs = 8 g 0.244 m_gn magnetic sensitivity magnetic fs = 16 gauss 0.58 mgauss/ lsb la_tcso linear acceleration sensitivity change vs. temperature 0.01 %/c la_tyoff typical zero- g level offset accuracy (3),(4) 40 m g m_tyoff typical zero- gauss level offset accuracy 1 gauss la_tcoff zero- g level change vs. temp. max. delta from 25 c 0.5 m g /c la_an linear acceleration rms noise odr = 100 hz, bw = 50 hz, fs = 2 g 1 m g (rms) m_r magnetic rms noise ultra-high-performance mode 3.5 mgauss (rms) df magnetic disturbance field zero-gauss offset starts to degrade 50 gauss la_st linear acceleration self-test positive difference (5) 70 1500 mg m_st magnetic self-test (6) x, y-axis -1 -3 gauss z-axis -0.1 -1 top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. verified by wafer level test and measurement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. offset can be eliminated by enabling the built-in high-pass filter. 5. accelerometer ?self-test positive difference? is defined as: output[mg] (ctrl_reg5_a st2, st1 bits=01) - output[mg] ( ctrl_reg5_a st2, st1 bits=00 ) . 6. magnetic ?self-test? is defined as: output[gauss] (ctrl_reg1_m st bit=1) - output[gauss] ( ctrl_reg1_m st bit=0 ) .
module specifications lsm303c 12/53 docid024975 rev 2 2.2 temperature sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (b) . 2.3 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted. (b) b. the product is factory calibrated at 2.5 v.the operational power supply range is from 1.9 v to 3.6 v. table 4. temperature sensor characteristics symbol parameter test conditions min. typ. (1) max. unit tsdr temperature sensor output change vs. temp. 8 digit/c todr temperature refresh rate (2) odr hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. if the temp_en bit in ctrl_reg1_m (20h) is set to ?1?, temperature data is acquired at each conversion cycle. refer to table 73: output data rate configuration table 5. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 1.9 3.6 v vdd_io module power supply for i/o 1.71 1.8 vdd+0.1 v la_idd_nm linear acceleration current consumption in active mode. magnetic sensor in power-down mode. odr = 100 - 800 hz 180 a odr = 50 hz 120 odr =10 hz 50 m_idd_hr magnetic current consumption in ultra-high resolution mode linear acceleration in power-down mode. odr = 20 hz 270 a m_idd_lp magnetic current consumption in low-power mode linear acceleration in power-down mode. odr = 20 hz 40 a idd_pd current consumption in power-down 6 a t op operating temperature range -40 +85 c trise time for power supply rising (2) 0.01 100 ms twait time delay between vdd_io and vdd (2) 010ms 1. typical specifications are not guaranteed . 2. please refer to section 2.3.1: recommended power-up sequence for more details.
docid024975 rev 2 13/53 lsm303c module specifications 53 2.3.1 recommended power-up sequence for the power-up sequence please refer to the following figure, where: ? trise is the time for the power supply to rise from 10% to 90% of its final value ? twait is the time delay between the end of the vdd_io ramp (90% of its final value) and the start of the vdd ramp figure 3. recommended power-up sequence
module specifications lsm303c 14/53 docid024975 rev 2 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 4. spi slave timing diagram note: values are guaranteed at 10 mhz clock frequency for spi with 3 wires, based on characterization results, not tested in production. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. table 6. spi slave timing values symbol parameter value ( 1 ) unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs_xl, cs_mag) cs setup time 6 ns t h(cs_xl, cs_mag) cs hold time 8 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 9 t dis(so) sdo output disable time 50 spc cs sdi sdo t su(cs_xl, cs_mag) t v(so) t h(so) t h(si) t su(si) t h(cs_xl, cs_mag) t dis(so) t c(spc) msb in msb out lsb out lsb in
docid024975 rev 2 15/53 lsm303c module specifications 53 2.4.2 i 2 c - inter-ic control interface subject to general operating conditions for vdd and top. figure 5. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production sd a scl t su(sp) t w(scll) t su(sda) t su(sr) t h(st) t w(sclh) t h(sda) t w(sp:sr) start repea ted sta rt stop sta rt
module specifications lsm303c 16/53 docid024975 rev 2 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (cs_xl, cs_mag, scl/spc, sda/sdi/sdo) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3000 for 0.5 ms g 10000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3000 for 0.5 ms g 10000 for 0.1 ms g m ef maximum exposed field 1000 gauss t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection (hbm) 2 kv this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part
docid024975 rev 2 17/53 lsm303c terminology 53 3 terminology 3.1 sensitivity 3.1.1 linear acceleration sensor sensitivity sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. as the sensor can measure dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 3.1.2 magnetic sensor sensitivity sensitivity describes the gain of the sensor and can be determined, for example, by applying a magnetic field of 1 gauss to it. 3.2 zero- g level the zero- g level offset (la_tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g for the x-axis and 0 g for the y-axis whereas the z-axis will measure 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as two?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little with temperature, see table 3 ?zero- g level change vs. temperature? (la_tcoff). the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. 3.3 zero- gauss level zero- g auss level offset (m_tyoff) describes the deviation of an actual output signal from the ideal output if no magnetic field is present.
functionality lsm303c 18/53 docid024975 rev 2 4 functionality 4.1 self-test the self-test allows checking the linear acceleration functionality without moving it. the self- test function is off when the self-test bits (st) are programmed to ?00?. when the self-test bits are changed, an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. when the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test force. if the output signals change within the amplitude limits specified inside table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. the self-test function is also available for the magnetic sensor. when the magnetic self-test is enabled, a current is forced into a coil near the sensor. this current will generate a magnetic field that will produce a variation of the magnetometer output signals. if the output signals change within the amplitude limits specified in table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 4.2 fifo the lsm303c embeds an acceleration data fifo for each of the three output channels, x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work accordingly to the following different modes: bypass mode, fifo mode, stream mode, stream-to-fifo mode, bypass-to-stream, bypass-to-fifo. each mode is selected by the fifo_mode bits in the fifo_ctrl register. programmable fifo threshold level, fifo empty or fifo overrun events are in the fifo_src register and can be set to generate a dedicated interrupt on the int_xl pin. fifo_src (empty) is equal to '1' when no samples are available. fifo_src (fth) goes to '1' if new data arrives and fifo_src(fss [4:0]) is greater than or equal to fifo_ctrl (fth [4:0]). fifo_src (fth) goes to '0' if reading a x, y, z data slot from fifo and fifo_src (fss [4:0]) is less than or equal to fifo_ctrl (fth [4:0]). fifo_src (ovr) is equal to '1' if a fifo slot is overwritten. the fifo feature is enabled by writing a '1' to the fifo_en bit in ctrl_reg3_a. to guarantee the correct acquisition of data during the switching into and out of fifo, the first sample acquired must be discarded. 4.2.1 bypass mode in bypass mode (fifo_ctrl (fmode [2:0])= 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo mode.
docid024975 rev 2 19/53 lsm303c functionality 53 4.2.2 fifo mode in fifo mode (fifo_ctrl (fmode [2:0]) = 001) data from the x, y and z channels are stored in the fifo until it is full. an overrun interrupt can be enabled, ctrl_reg3_a (int_xl_ovr) = '1', in order to be raised when the fifo stops collecting data. when the overrun interrupt occurs, the first set of data has been overwritten and the fifo stops collecting data from the input channels. to reset the fifo content, bypass mode should be written in fifo_ctrl (fmode [2:0]) as '000'. after this reset command it is possible to restart fifo mode by writing '001' to fifo_ctrl (fmode [2:0]). the fifo buffer can memorize 32 levels of x, y and z data, but the depth of the fifo can be reduced by means of the ctrl_reg3_a (stop_ fth) bit. setting the stop_fth bit to '1', the fifo depth is limited to fifo_ctrl (fth [4:0]) - 1. 4.2.3 stream mode stream mode (fifo_ctrl (fmode [2:0]) = 010) provides a continuous fifo update. as new data arrives the older data is discarded. an overrun interrupt can be enabled, ctrl_reg3_a (int_xl_ovr) = '1', in order to read the entire content of the fifo at once. if in the application no data can be lost and it is not possible to read at least one sample for each axis within one odr period, a watermark interrupt can be enabled in order to read partially the fifo and leave free memory slots for incoming data. setting the fifo_ctrl (fth [4:0]) to an n value, the number of x, y and z data samples that should be read at the rise of the watermark interrupt is up to (n+1). in the latter case, reading all fifo content before an overrun interrupt has occurred, the first data read is equal to the last data already read in the previous burst, so the number of new data available in fifo depends on the previous reading (see fifo_src behavior depicted in the following figure). figure 6. stream mode stream mode is intended to be used to read all 32 samples of fifo within an odr after receiving an overrun signal.
functionality lsm303c 20/53 docid024975 rev 2 a watermark interrupt ctrl_reg3_a (int_xl_fth) can be enabled in order to read data from the fifo and leave a free memory slot for incoming data. setting the fifo_ctrl (fth [4:0]) to an n value, the number of x, y and z data samples that should be read at the rise of the watermark interrupt, in order to read the entire content of the fifo, is n + 1. 4.2.4 stream-to-fifo mode in stream-to-fifo mode (fifo_ctrl(fmode2:0) = 011), fifo behavior changes according to the ig_src1_a (ia) bit. when the ig_src1_a(ia) bit is equal to '1', fifo operates in fifo mode, when the ig_src1_a (ia) bit is equal to '0', fifo operates in stream mode. the interrupt generator 1 should be set to the desired configuration by means of ig_cfg1_a, ig_ths_x1_a, ig_ths_y1_a and ig_ths_z1_a. the ctrl_reg7_a (lir1) bit should be set to '1' in order to have latched interrupt. 4.2.5 bypass-to-stream mode in bypass-to-stream mode (fifo_ctrl (fmode [2:0]) = '100'), x, y and z measurement storage inside fifo operates in stream mode when the ig_src1_a (ia) is equal to '1', otherwise fifo content is reset (bypass mode). the interrupt generator 1 should be set to the desired configuration by means of ig_cfg1_a, ig_ths_x1_a, ig_ths_y1_a and ig_ths_z1_a. the ctrl_reg7_a (lir1) bit should be set to '1' in order to have latched interrupt. 4.2.6 bypass-to-fifo mode in bypass-to-fifo mode (fifo_ctrl (fmode [2:0]) = '111', fifo behavior changes according to the ig_src1_a(ia) bit. when the ig_src1_a(ia) bit is equal to '1,' fifo operates in fifo mode. when the ig_src1_a(ia) bit is equal to '0', fifo operates in bypass mode (fifo content reset). if a latched interrupt is generated, fifo starts collecting data until the first data into the fifo buffer is overwritten. the interrupt generator 1 should be set to the desired configuration by means of ig_cfg1_a, ig_ths_x1_a, ig_ths_y1_a and ig_ths_z1_a. the ctrl_reg7_a (lir1) bit should be set to '1' in order to have latched interrupt. 4.2.7 retrieving data from fifo fifo data is read from the out_x_a, out_y_a and out_z_a registers. a read operation using a serial interface of the out_x_a, out_y_a or out_z_a output registers provides the data stored in the fifo. each time data is read from the fifo, the oldest x, y and z data are placed in the out_x_a, out_y_a and out_z_a registers and both single read and read_burst operations can be used. 4.2.8 fifo multiple read (burst) starting from addr 28h multiple reads can be performed. once the read reaches addr 2dh the system automatically restarts from addr 28h.
docid024975 rev 2 21/53 lsm303c functionality 53 figure 7. fifo multiple read 4.3 activity/inactivity function the activity/inactivity recognition function allows reducing the power consumption of the accelerometer block in order to supply other smart applications. when the activity/inactivity recognition function is activated, accelerometer is able to automatically go to 10 hz sampling rate and to wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature the system may be efficiently switched from/to low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility. the activity/inactivity recognition function is activated by writing the desired threshold in the act_ths_a register. the high-pass filter is automatically enabled. table 9. activity/inactivity function control registers when the acceleration becomes smaller than the threshold for at least (8 act_dur +1)/odr time, the ctrl_reg1_a (odr [2:0]) bits of ctrl_reg1_a are bypassed (inactivity) and internally set to 10 hz (odr [2:0] = 001), but the content of the ctrl_reg1_a (odr [2:0]) bits are left untouched. when the acceleration becomes bigger than the threshold (act_ths_a), ctrl_reg1_a is restored immediately (activity). once the activity/inactivity detection function is enabled, it will be applied to the int_xl pin by setting the ctrl_reg3_a (int_xl_inact) bit to ?1?. to disable the activity/inactivity detection function, set the content of act_ths_a register to 00h. 4.4 factory calibration the ic interface is factory calibrated for sensitivity (la_so, m_gn), zero- g level (la_tyoff) and zero- gauss level (m_tyoff). the trim values are stored inside the device in non-volatile memory. anytime the device is turned on, the trim parameters are downloaded into the registers to be used during active operation. this allows using the device without further calibration. x,y,z out_z_a read #1 (2c-2d) (2a-2b) out_y_a (28-29) out_x_a x,y,z read #n out_z_a (2c-2d) (2a-2b) out_y_a (28-29) out_x_a register lsb value act_ths_a full scale / 128 [mg] act_dur_a 8/odr [s]
application hints lsm303c 22/53 docid024975 rev 2 5 application hints figure 8. lsm303c electrical connections the device core is supplied through the vdd line while the i/o pads are supplied through the vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to pin 9 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 8 ). it is possible to remove vdd, maintaining vdd_io, without blocking the communication bus, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data are selectable and accessible through the i 2 c or spi interfaces. when using the i 2 c, cs must be tied high (i.e. connected to vdd_io). the functions, the threshold and the timing of the two interrupt pins (int_xl and int_mag) can be completely programmed by the user through the i 2 c/spi interface. 5.1 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standards. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www .st.com . digital signal from/to signal controller. signal levels are defined by proper selection of vdd_io. vdd_io c 2 =10f vdd c 3 =100nf gnd c1 sc l/spc sda/sdi/sdo cs_xl cs_mag gnd gnd drdy_mag vdd_io 4 1 6 5 int_mag 12 11 int_xl 7 10 vdd c 4 =100nf c 1 =100nf top view
docid024975 rev 2 23/53 lsm303c application hints 53 5.2 high current wiring effects high current in wiring and printed circuit traces can be culprits in causing errors in magnetic field measurements for compassing. conductor-generated magnetic fields will add to the earth?s magnetic field, leading to errors in compass heading computation. keep currents higher than 10 ma a few millimeters away from the sensor ic.
digital interfaces lsm303c 24/53 docid024975 rev 2 6 digital interfaces the registers embedded inside the lsm303c may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw-configured to operate in 3-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.1 i 2 c serial interface the lsm303c i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines must be connected to vdd_io through an external pull- up resistor. when the bus is free, both the lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with the normal mode. in order to disable the i 2 c block for the accelerometer, ctrl_reg4_a (i2c_disable) must be written to ?1?, while for magnetometer ctrl_reg3_m (i2c_disable) must be written to ?1?. table 10. serial interface pin description pin name pin description cs_xl, cs_mag spi enable i2c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) table 11. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
docid024975 rev 2 25/53 lsm303c digital interfaces 53 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the lsm303c behaves like a slave device and the following protocol must be adhered to. in the i 2 c of the accelerometer sensor, after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted. the 7 lsb represent the actual register address while the ctrl_reg4_a (if_add_inc) bit defines the address increment. in the i 2 c of the magnetometer sensor, after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted. the 7 lsb represent the actual register address while the msb enables the address auto increment. the sub (register address) is automatically increased to allow multiple data read/write. data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 13. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 14. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a data
digital interfaces lsm303c 26/53 docid024975 rev 2 (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. default address: the accelerometer sensor slave address is 0011101b while magnetic sensor slave address is 0011110b. the slave addresses are completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes. if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 16 and table 17 explain how the sad+read/write bit pattern are composed, listing all the possible configurations. linear acceleration sensor: the default (factory setting) 7-bit slave address is 0011101b. table 16. sad + read/write patterns magnetic field sensor: the default (factory setting) 7-bit slave address is 0011110b. table 17. sad + read/write patterns 6.2 spi bus interface the lsm303c spi is a bus slave. the spi allows writing and reading the registers of the device. the serial interface interacts with the outside world with 3 wires: cs_xl , cs_mag, spc , sdi . 3-wire mode is entered by setting the ctrl_reg4_a (sim) and ctrl_reg3_m (sim) bit equal to ?1? (spi serial interface mode selection). command sad[6:0] r/w sad + r/w read 0011101 1 00111011 (3bh) write 0011101 0 00111010 (3ah) command sad[6:0] r/w sad + r/w read 001110 1 00111101 (3dh) write 001110 0 00111100 (3ch)
docid024975 rev 2 27/53 lsm303c digital interfaces 53 6.2.1 accelerometer spi write figure 9. accelerometer spi write protocol the spi write command is performed with 16 clock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 -7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 10. multiple byte spi write protocol (2-byte example) 6.2.2 accelerometer spi read in 3-wire mode figure 11. accelerometer spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ad6 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ad6 cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ad6
digital interfaces lsm303c 28/53 docid024975 rev 2 bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). the multiple read command is available in 3-wire mode. 6.2.3 magnetometer spi write figure 12. magnetometer spi write protocol the spi write command is performed with 16 clock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : m s bit. when 0 does not increment the address; when 1, increments the address in multiple writes. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 13. multiple byte spi write protocol (2-byte example) cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad 4 ad 3 ad2 ad 1 ad0 ms am10132v1 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 13 d i1 2 di 11 di 10 di 9 di 8 ms am10133v1
docid024975 rev 2 29/53 lsm303c digital interfaces 53 6.2.4 magnetometer spi read figure 14. magnetometer spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). the multiple read command is available in 3-wire mode. cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad 4 ad 3 ad2 ad1 ad 0 ms am10134v1
register mapping lsm303c 30/53 docid024975 rev 2 7 register mapping the table given below provides a listing of the 8/16 bit registers embedded in the accelerometer and the corresponding address. table 18. accelerometer register address map name type register address default comment hex binary reserved r 00-0e - reserved who_am_i_a r of 00001111 01000001 accelerometer who i am id act_ths_a r/w 1e 00011110 00000000 act_dur_a r/w 1f 0001 1111 00000000 ctrl_reg1_a r/w 20 00100000 00000111 accelerometer control registers ctrl_reg2_a r/w 21 00100001 00000000 ctrl_reg3_a r/w 22 00100010 00000000 ctrl_reg4_a r/w 23 00100011 00000100 ctrl_reg5_a r/w 24 00100100 00000000 ctrl_reg6_a r/w 25 00100101 00000000 ctrl_reg7_a r/w 26 00100110 00000000 status_reg_a r 27 00100111 output accelerometer status data register out_x_l_a r 28 00101000 output accelerometer output registers out_x_h_a r 29 00101001 out_y_l_a r 2a 00101010 out_y_h_a r 2b 00101011 out_z_l_a r 2c 00101100 out_z_h_a r 2d 00101101 fifo_ctrl r/w 2e 00101110 00000000 accelerometer fifo registers fifo_src r 2f 00101111 output ig_cfg1_a r/w 30 00110000 00000000 accelerometer interrupt generator 1 configuration ig_src1_a r 31 00110001 output accelerometer interrupt generator 1 status register ig_ths_x1_a r/w 32 00110010 00000000 accelerometer interrupt generator 1 threshold x ig_ths_y1_a r/w 33 00110011 00000000 accelerometer interrupt generator 1 threshold y ig_ths_z1_a r/w 34 00110100 00000000 accelerometer interrupt generator 1 threshold z
docid024975 rev 2 31/53 lsm303c register mapping 53 table 19. magnetic sensor register address map: ig_dur1_a r/w 35 00110101 00000000 accelerometer interrupt generator 1 duration ig_cfg2_a r/w 36 00110110 00000000 accelerometer interrupt generator 2 configuration ig_src2_a r 37 00110111 output accelerometer interrupt generator 2 status register ig_ths2_a r/w 38 00111000 00000000 accelerometer interrupt generator 2 threshold ig_dur2_a r/w 39 00111001 00000000 accelerometer interrupt generator 2 duration xl_reference r/w 3a 00111010 00000000 reference x low xh_reference r/w 3b 00111011 00000000 reference x high yl_reference r/w 3c 00111100 00000000 reference y low yh_reference r/w 3d 00111101 00000000 reference y high zl_reference r/w 3e 001 11110 00000000 reference z low zh_reference r/w 3f 00111111 00000000 reference z high name type register address default comment hex binary reserved 00 - 0e -- -- reserved who_am_i_m r 0f 0000 1111 00111101 magnetic who i am id reserved 10 - 1f -- -- reserved ctrl_reg1_m r/w 20 0010 0000 00010000 magnetic control registers ctrl_reg2_m r/w 21 0010 0001 00000000 ctrl_reg3_m r/w 22 0010 0010 00000011 ctrl_reg4_m r/w 23 0010 0011 00000000 ctrl_reg5_m r/w 24 0010 0100 00000000 reserved 25 - 26 -- -- reserved status_reg_m r 27 0010 0111 output out_x_l_m r 28 0010 1000 output magnetic output registers out_x_h_m r 29 0010 1001 output out_y_l_m r 2a 0010 1010 output out_y_h_m r 2b 0010 1011 output out_z_l_m r 2c 0010 1100 output out_z_h_m r 2d 0010 1101 output name type register address default comment hex binary
register mapping lsm303c 32/53 docid024975 rev 2 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory-calibrated values. their content is automatically restored when the device is powered up. temp_l_m r 2e 0010 1110 output temp_h_m r 2f 0010 1111 output int_cfg_m rw 30 00110000 00001000 magnetic interrupt configuration register int_src_m r 31 00110001 00000000 magnetic interrupt generator status register int_ths_l_m r 32 00110010 00000000 magnetic interrupt generator threshold int_ths_h_m r 33 00110011 00000000 name type register address default comment hex binary
docid024975 rev 2 33/53 lsm303c register description 53 8 register description 8.1 who_am_i_a (0fh) accelerometer who_am_i register (r). this register is a read-only register. its default value is 41h. 8.2 act_ths_a (1eh) activity threshold register (r/w). its default value is 0x00. inactivity threshold. 8.3 act_dur_a (1fh) activity duration register (r/w). its default value is 0x00. activity duration. 8.4 ctrl_reg1_a (20h) accelerometer control register 1 (r/w) table 23. ctrl_reg1_a register table 24. ctrl_reg1_a register description table 20. who_am_i_a register default value 01000001 table 21. act_ths_a register - ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 22. act_dur_a register dur7 dur6 dur5 dur4 dur3 dur2 dur1 dur0 hr odr2 odr1 odr0 bdu zen yen xen hr high-resolution bit. default value: 0 0: normal mode, 1: high resolution (see table 26 ) odr [2:0] output data rate & power mode selection . default value: 000 (see table 25 ) bdu block data update. default value:0 0: continuous update,1:output registers not updated until msb and lsb read) zen z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) yen y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) xen x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled)
register description lsm303c 34/53 docid024975 rev 2 odr [2:0] is used to set power mode and odr selection. all frequencies available are given in the following table. the bdu bit is used to inhibit the update of the output registers until both upper and lower register parts are read. in default mode (bdu = ?0?) the output register values are updated continuously. when the bdu is activated (bdu = ?1?), the content of the output registers is not updated until both msb and lsb are read which avoids reading values related to different sample times. 8.5 ctrl_reg2_a (21h) accelerometer control register 2 (r/w) table 27. ctrl_reg2_a register table 28. ctrl_reg2_a register description table 25. odr register setting odr2 odr1 odr0 odr selection 0 0 0 power down 0 0 1 10 hz 0 1 0 50 hz 0 1 1 100 hz 1 0 0 200 hz 1 0 1 400 hz 1 1 0 800 hz 1 1 1 n.a. table 26. low-pass cutoff frequency in high-resolution mode (hr = 1) hr ctrl_reg2_a (dfc [1:0]) lp cutoff freq. [hz] 1 00 odr/50 1 01 odr/100 1 10 odr/9 1 11 odr/400 - dfc1 dfc0 hpm1 hpm0 fds hpis2 hpis1 dfc1 [1:0] high-pass filter cutoff frequency selection: the bandwidth of the high-pass filter depends on the selected odr and on the settings of the dfc [1:0] bits hpm [1:0] high-pass filter mode selection. default value: 00 ?00? or ?10? = normal mode ?01? = reference signal for filtering ?11? = not available
docid024975 rev 2 35/53 lsm303c register description 53 8.6 ctrl_reg3_a (22h) accelerometer control register 3 (r/w). int_xl control register table 29. ctrl_reg3_a register table 30. ctrl_reg3_a register description 8.7 ctrl_reg4_a (23h) accelerometer control register 4 (r/w) table 31. ctrl_reg4_a register fds high-pass filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) hpis [2:1] high pass filter enabled for interrupt generator function on interrupt 2 and interrupt 1 (0: filter bypassed; 1: filter enabled) fifo_en stop_fth int_xl _inact int_xl _ig2 int_xl _ig1 int_xl _ovr int_xl _fth int_xl _drdy fifo_en fifo enable. default value 0. (0: disable; 1: enable) stop_fth enable fifo threshold level use. default value 0. (0: disable; 1: enable) int_xl_inact inactivity interrupt on int_xl. default value 0. (0: disable; 1: enable) int_xl_ig2 interrupt generator 2 on int_xl. default value 0. (0: disable; 1: enable) int_xl_ig1 interrupt generator 1 on int_xl. default value 0. (0: disable; 1: enable) int_xl_ovr fifo overrun signal on int_xl int_xl_fth fifo threshold signal on int_xl int_xl_drdy data ready signal on int_xl bw2 bw1 fs1 fs0 bw_scale_odr if_add_inc i2c_disable sim table 32. ctrl_reg4_a register description bw [2:1] anti aliasing filter bandwidth. default value: 00 (00: 400 hz; 01: 200 hz; 10: 100 hz; 11: 50 hz) fs [1:0] full-scale selection. default value: 00 (00: 2 g ; 01: not available; 10: 4 g ; 11: 8 g )
register description lsm303c 36/53 docid024975 rev 2 8.8 ctrl_reg5_a (24h) control register 5 (r/w) table 33. ctrl_reg5_a register bw_scale _odr if '0' bandwidth is automatically selected according bw = 400 hz when odr = 800 hz, 50 hz, 10 hz; bw = 200 hz when odr = 400 hz; bw = 100 hz when odr = 200 hz; bw = 50 hz when odr = 100 hz; if '1' bandwidth is selected according to bw [2:1] excluding odr = 50 hz, 10 hz, bw = 400 hz if_add_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). (0: disable; 1: enable) i2c_disable disable i 2 c interface. default value 0. (0: i 2 c enable; 1: i 2 c disable) sim spi serial interface mode selection. default value: 0 0 = spi write-only operations enabled; 1 = spi read and write operations enabled table 32. ctrl_reg4_a register description debug soft_reset dec1 dec0 st2 st1 h_lactive pp_od table 34. ctrl_reg5_a register description debug debug stepping action selected. default value: 0 (0: disable; 1: enable) soft_reset soft reset, it acts as por when 1, then goes to 0 dec [1:0] decimation of acceleration data on out reg and fifo 00: no decimation 01: update every 2 samples 10: update every 4 samples 11: update every 8 samples st [2:1] self-test enable. default value: 00 (00: self-test disabled; other: see table 35 ) h_lactive interrupt active high, low. default value: 0 (0: active high; 1: active low) pp_od push-pull/open-drain selection on interrupt pad. default value: 0 (0: push-pull; 1: open drain) table 35. self-test mode selection st2 st1 self-test mode 0 0 normal mode 0 1 positive sign self-test 1 0 negative sign self-test 1 1 not allowed
docid024975 rev 2 37/53 lsm303c register description 53 8.9 ctrl_reg6_a (25h) accelerometer control register 6 (r/w) 8.10 ctrl_reg7_a (26h) accelerometer control register 7 (r/w) table 38. ctrl_reg7_a register 8.11 status_reg_a (27h) accelerometer status register (r/w) table 40. status_reg_a register table 36. ctrl_reg6_a register boot ------- table 37. ctrl_reg6_a register description boot force reboot, cleared as soon as the reboot is finished. active high. default value 0. - - dcrm2 dcrm1 lir2 lir1 4d_ig2 4d_ig1 table 39. ctrl_reg7_a register description dcrm [2:1] dcrm is used to select the reset mode of the duration counter. default value 0. if dcrm = ?0?, the counter is reset when the interrupt is no longer active, else if dcrm = ?1?, the duration counter is decremented. 1 lsb lir [2:1] latched interrupt [2:1] default value:0 (0: interrupt request not latched; 1: interrupt request latched) cleared by reading ig_src[2:1]_a register 4d_ig [2:1] interrupt [2:1] 4d option enabled. default value 0. when set, interrupt generator [2:1] uses 4d for position recognition. zyxor zor yor xor zyxda zda yda xda table 41. status_reg_a register description zyxor x, y and z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous data) zor z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data for the z-axis has overwritten the previ- ous data)
register description lsm303c 38/53 docid024975 rev 2 8.12 out_x_l_a (28h), out_x_h_a (29h) accelerometer x-axis output register (r) table 42. out_x_l_a register default values table 43. out_x_h_a register default values 8.13 out_y_l_a (2ah), out_y_h_a (2bh) accelerometer y-axis output register (r) table 44. out_y_l_a register default values table 45. out_y_h_a register default values 8.14 out_z_l_a (2ch), out_z_h_a (2dh) accelerometer z-axis output register (r) table 46. out_z_l_a register default values table 47. out_z_h_a register default values yor y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x, y and z-axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available) table 41. status_reg_a register description (continued) 00000000 00000000 00000000 00000000 00000000 00000000
docid024975 rev 2 39/53 lsm303c register description 53 8.15 fifo_ctrl (2eh) fifo control register (r/w) table 48. fifo_ctrl register the fifo trigger is the interrupt generator 1 event, all related information is available in section 8.18: ig_src1_a (31h) . 8.16 fifo_src (2fh) fifo status control register (r) table 51. fifo_src register table 52. fifo_src register description fmode2 fmode1 fmode0 fth4 fth3 fth2 fth1 fth0 table 49. fifo_ctrl register description fmode [2:0] fifo mode selection bits. default 000. for further details refer to table 50 fth [4:0] fifo threshold. default: 00000. it is the fifo depth if the stop_fth bit in the ctrl3 (22h) register is set to ?1?. table 50. fifo mode selection fmode2 fmode1 fmode0 mode 0 0 0 bypass mode. fifo turned off 0 0 1 fifo mode. stops collecting data when fifo is full. 0 1 0 stream mode. if the fifo is full, the new sample overwrites the older one 0 1 1 stream mode until trigger is deasserted, then fifo mode 1 0 0 bypass mode until trigger is deasserted, then stream mode 1 0 1 not used 1 1 0 not used 1 1 1 bypass mode until trigger is deasserted, then fifo mode fth ovr empty fss4 fss3 fss2 fss1 fss0 fth fifo threshold status. 0: fifo filling is lower than fth level; 1: fifo filling is equal or higher than threshold level ovr overrun bit status. 0: fifo is not completely filled; 1: fifo is completely filled empty fifo empty bit. 0: fifo not empty; 1: fifo empty) fss [4:0] fifo stored data level
register description lsm303c 40/53 docid024975 rev 2 8.17 ig_cfg1_a (30h) accelerometer interrupt generator 1 configuration register (r/w) table 53. ig_cfg1_a register table 54. ig_cfg1_a register description 8.18 ig_src1_a (31h) accelerometer interrupt generator 1 status register (r) table 55. ig_src1_a register table 56. ig_src1_a register description aoi 6d zhie zlie yhie ylie xhie xlie aoi and/or combination of interrupt events. default value: 0. 6d 6 direction detection function enabled. default value: 0. zhie enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) ylie enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xhie enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xlie enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) - ia zhzlyhylxhxl ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events has been generated) zh z high. default value: 0 (0: no interrupt; 1: zh event has occurred) zl z low. default value: 0 (0: no interrupt; 1: zl event has occurred) yh y high. default value: 0 (0: no interrupt; 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt; 1: yl event has occurred) xh x high. default value: 0 (0: no interrupt; 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt; 1: xl event has occurred)
docid024975 rev 2 41/53 lsm303c register description 53 8.19 ig_ths_x1_a (32h), ig_ths_y1_a (33h), ig_ths_z1_a (34h) accelerometer interrupt generator 1 threshold registers (r/w) table 57. ig_ths register table 58. ig_ths register description 8.20 ig_dur1_a (35h) accelerometer interrupt generator 1 duration register (r/w) table 59. ig_dur1_a register table 60. ig_dur1_a register description 8.21 ig_cfg2_a (36h) accelerometer interrupt generator 2 configuration register (r/w) table 61. ig_cfg2_a register table 62. ig_cfg2_a register description ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 ths [7:0] interrupt 1 threshold. default 00000000. wait1 dur1_6 dur1_5 dur1_4 dur1_3 dur1_2 dur1_1 dur1_0 wait1 wait function enable on duration counter. default value: 0 (0: wait function off; 1: wait function on) dur1_[6:0] duration value. default 0000000. aoi 6d zhie zlie yhie ylie xhie xlie aoi and/or combination of interrupt events. default value: 0. 6d 6-direction detection function enabled. default value: 0. zhie enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) ylie enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) xhie enable interrupt generation on xlow event or on direction recognition. default value: 0 (0: disable interrupt request;1: enable interrupt request) xlie enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request;1: enable interrupt request)
register description lsm303c 42/53 docid024975 rev 2 8.22 ig_src2_a (37h) accelerometer interrupt generator 2 status register (r) table 63. ig_src2_a register table 64. ig_src2_a register description 8.23 ig_ths2_a (38h) accelerometer interrupt generator 2 threshold register (r/w) table 65. ig_ths2_a register table 66. ig_ths2_a register description 8.24 ig_dur2_a (39h) accelerometer interrupt generator 2 duration register (r/w) table 67. ig_dur2_a register table 68. ig_dur2_a register description - ia zhzlyhylxhxl ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events has been generated) zh z high. default value: 0 (0: no interrupt; 1: zh event has occurred) zl z low. default value: 0 (0: no interrupt; 1: zl event has occurred) yh y high. default value: 0 (0: no interrupt; 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt; 1: yl event has occurred) xh x high. default value: 0 (0: no interrupt; 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt; 1: xl event has occurred) ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 ths [7:0] interrupt generator 2 threshold. default 00000000. wait2 dur2_6 dur2_5 dur2_4 dur2_3 dur2_2 dur2_1 dur2_0 wait2 wait function enable on duration counter. default value: 0 (0: wait function off; 1: wait function on) dur2_[6:0] duration value. default 0000000.
docid024975 rev 2 43/53 lsm303c register description 53 8.25 xl_reference (3ah), xh_reference (3bh) in normal mode (hpm [1:0] = ?00? or ?10?) when one of these registers (xl_reference or xh_reference) is read, the x output of the hp filter is set to ?0?. in reference mode (hpm [1:0] =?01?) the reference value is subtracted from the x output of the hp filter. 8.26 yl_reference (3ch), yh_reference (3dh) see above comment for x reference (r/w). 8.27 zl_reference (3eh), zh_reference (3fh) see above comment for x reference (r/w). 8.28 who_am_i_m (0fh) device identification register. 8.29 ctrl_reg1_m (20h) table 72. x and y axes operative mode selection table 69. who_am_i_m register 00111101 table 70. ctrl_reg1_m register temp_en om1 om0 do2 do1 do0 0 (1) 1. this bit must be set to ?0? for the correct operation of the device st table 71. ctrl_reg1_m register description temp_en temperature sensor enable. default value: 0 (0: temperature sensor disabled; 1: temperature sensor enabled) om[1:0] x and y axes operative mode selection. default value: 00 (refer to table 72 ) do[2:0] output data rate selection. default value: 100 (refer to table 73 ) st self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled) om1 om0 operative mode for x and y axes 0 0 low-power mode 0 1 medium-performance mode 1 0 high-performance mode 1 1 ultra-high performance mode
register description lsm303c 44/53 docid024975 rev 2 table 73. output data rate configuration 8.30 ctrl_reg2_m (21h) 8.31 ctrl_reg3_m (22h) do2 do1 do0 odr [hz] 0 0 0 0.625 0 0 1 1.25 0 1 0 2.5 0115 1 0 0 10 1 0 1 20 1 1 0 40 1 1 1 80 table 74. ctrl_reg2_m register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device fs1 fs0 0 (1) reboot soft_rst 0 (1) 0 (1) table 75. ctrl_reg2_m register description fs[1:0] full-scale configuration. default value: 00 refer to table 76 reboot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) soft_rst configuration registers and user register reset function. (0: default value; 1: reset operation) table 76. full-scale selection fs1 fs0 full scale 0 0 not used 0 1 not used 1 0 not used 1 1 16 gauss table 77. ctrl_reg3_m register i2c_disa ble 0 (1)) 1. these bits must be set to ?0? for the correct operation of the device. lp 0 (1) 0 (1) sim md1 md0
docid024975 rev 2 45/53 lsm303c register description 53 table 79. system operating mode selection 8.32 ctrl_reg4_m (23h) table 82. z-axis operative mode selection table 78. ctrl_reg3_m register description i2c_disable disable i 2 c interface. default value 0. (0: i 2 c enable; 1: i 2 c disable) lp low-power mode configuration. default value: 0 if this bit is ?1?, the do[2:0] is set to 0.625 hz and the system performs, for each channel, the minimum number of averages. once the bit is set to ?0?, the magnetic data rate is configured by the do bits in ctrl_reg1_m (20h) register. sim spi serial interface mode selection. default value: 0 (0= spi only write operations enabled; 1= spi read and write operations enable). md[1:0] operating mode selection. default value: 11 refer to table 79. md1 md0 mode 0 0 continuous-conversion mode 0 1 single-conversion mode single-conversion mode has to be used with sampling frequency from 0.625 hz to 80 hz. 1 0 power-down mode 1 1 power-down mode table 80. ctrl_reg4_m register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) 0 (1) omz1 omz0 ble 0 (1) table 81. ctrl_reg4_m register description omz[1:0] z-axis operative mode selection. default value: 00. refer to table 82. ble big/little endian data selection. default value: 0 (0: data lsb at lower address; 1: data msb at lower address) omz1 omz0 operative mode for z-axis 0 0 low-power mode 0 1 medium-performance mode 1 0 high-performance mode 1 1 ultra-high performance mode
register description lsm303c 46/53 docid024975 rev 2 8.33 ctrl_reg5_m (24h) 8.34 status_reg_m (27h) table 83. ctrl_reg5_m register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device. bdu 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) table 84. ctrl_reg5_m register description bdu block data update for magnetic data. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb have been read) table 85. status_reg_m register zyxor zor yor xor zyxda zda yda xda table 86. status_reg_m register description zyxor x, y and z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous data) zor z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x, y and z-axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x-axis new data available. default value: 0 (0: a new data for the x-axis is not yet available; 1: a new data for the x-axis is available)
docid024975 rev 2 47/53 lsm303c register description 53 8.35 out_x_l_m (28h), out_x_h_m(29h) magnetometer x-axis data output. the value of the magnetic field is expressed as two?s complement. 8.36 out_y_l_m (2ah), out_y_h_m (2bh) magnetometer y-axis data output. the value of the magnetic field is expressed as two?s complement. 8.37 out_z_l_m (2ch), out_z_h_m (2dh) magnetometer z-axis data output. the value of the magnetic field is expressed as two?s complement. 8.38 temp_l_m(2eh), temp_h_m (2fh) temperature sensor data. the value of the temperature is expressed as two?s complement. 8.39 int_cfg_m (30h) table 87. int_cfg_m register xien yien zien 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. 1 (2) 2. this bit must be set to ?1? for the correct operation of the device. iea iel ien table 88. int_cfg_m register description xien enable interrupt generation on x-axis. default value: 0 0: disable interrupt request; 1: enable interrupt request yien enable interrupt generation on y-axis. default value: 0 0: disable interrupt request; 1: enable interrupt request zien enable interrupt generation on z-axis. default value: 0 0: disable interrupt request; 1: enable interrupt request iea interrupt active configuration on int_mag. default value: 0 0: low; 1: high iel latch interrupt request. default value: 0 0: interrupt request latched; 1: interrupt request not latched) once latched, the int_mag pin remains in the same state until int_src_m (31h) ) is read. ien interrupt enable on the int_mag pin. default value: 0 0: disable; 1: enable
register description lsm303c 48/53 docid024975 rev 2 8.40 int_src_m (31h) table 89. int_src_m register pth_x pth_y pth_z nth_x nth_y nth_z mroi (1) 1. this functionality can be enabled only if the ien bit in int_cfg_m (30h) is enabled. int table 90. int_src_m register description pth_x value on x-axis exceeds the threshold on the positive side. default value: 0. pth_y value on y-axis exceeds the threshold on the positive side. default value: 0. pth_z value on z-axis exceeds the threshold on the positive side. default value: 0. nth_x value on x-axis exceeds the threshold on the negative side. default value: 0. nth_y value on y-axis exceeds the threshold on the negative side. default value: 0. nth_z value on z-axis exceeds the threshold on the negative side. default value: 0. mroi internal measurement range overflow on magnetic value. default value: 0. int this bit signals when the interrupt event occurs.
docid024975 rev 2 49/53 lsm303c register description 53 8.41 int_ths_l_m (32h), int_ths_h_m (33h) interrupt threshold. default value: 0. the value is expressed in 15-bit unsigned. even if the threshold is expressed in absolute value, the device detects both positive and negative thresholds. table 91. int_ths_l_m register ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 92. int_ths_h_m register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device. ths14 ths13 ths12 ths11 ths10 ths9 ths8
package information lsm303c 50/53 docid024975 rev 2 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. note: 1. dimensioning and tolerancing schemes conform to asme y14.5m-1994. 2. all dimensions are in millimeters. 3. the "pin 1 indicator" is identified on top and/or bottom surfaces of the package. 4. a1 is defined as the distance from the seating plane to the land. 5. "n" is the maximum number of terminal positions for the specified body size. 6. the tolerance of the typical value is specified in the table "tolerance of form and position". 7. dimensions "b" and "l" are specified: for solder mask defined: at terminal plating surface for non-solder mask defined: at solder mask opening table 93. lga-12 2x2x1 mm mechanical dimensions (see note 1 and 2) databook symbol min. typ. max. note ? - 45 - a - - 1.00 a1 0.00 - 0.05 4 a2 - 0.13 - b - 0.25 - 7 d 2.00 6 e 2.00 6 e 0.50 e1 1.50 h - 0.075 - l - 0.275 - 7 l1 - 0.10 - n125 symbol tolerance of form and position databook d/e 0.15 notes 1 and 2 ref -
docid024975 rev 2 51/53 lsm303c package information 53 figure 15. lga-12 2x2x1 mm mechanical drawing 8487209_a
revision history lsm303c 52/53 docid024975 rev 2 10 revision history table 94. document revision history date revision changes 12-jul-2013 1 initial release 13-jun-2014 2 document status promoted from preliminary data to production data added trise and twait to table 5: electrical characteristics added section 2.3.1: recommended power-up sequence
docid024975 rev 2 53/53 lsm303c 53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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